10-Sep-2001 Sasha RS TDC calibration based on kmu21 trigger
3-Sep-2001 Sasha Twalk correction based on cosmic trigger
28-Aug-2001 Erik Repair of non-working TDC
17-Aug-2001 Bob E949 status, CKM photon veto, Trigger installation
31-Jul-2001 Peter,Sasha RS TDC fixes
Wed Jun 6 13:15:23 CDT 2001 summary of Bob T & psc's BNL trip ---------------------------- I've upgraded LRS3377_init.c to read the module header ID from TDC.list. I copied the $CAMAC_COMMANDS/3377 directory an modified things there so that I don't hose either the online or CVS. This was tested and seems to work fine. I included an edited version of Sasha's rstdc_cabling.fig which documents the present layout in a figure. There is a copy of this on the website at Fermilab for Sasha to link into the website There is also a new command fcna in /e787d/bnlonl/fcna. This is a hack of camtest.f. It does the obvious thing from the shell level: fcna function crate slot sub-address I've asked George Redlinger to include these upgrades; I don't know enough yet to do it correctly myself. psc
06-Jun-2001 Bob RS TDC fixes, Installation of L1.1 trigger
27-May-2001 Sasha Study of RS TDC using pulser trigger
16-May-2001 Sasha Study of RS TDC kmu2 and kbeam data
Thu Apr 12 20:32:54 CDT 2001 power usage - psc and ak at BNL ---------------------------- Measured power usage of rstdc system crates and compared to the stated requirement from spec-sheets: Specs DSP 860p DYC LRS 3377 our crate CAMAC ps x2 x12 +6 <50a 1.5a 3.0a 1.1a 13.2a 16.2a -6 <50a 0.5a 1.0a 2.0a 24.0a 25.0a +/-6 <60a +24 <6a 0.025a 0.3a 0.3a -24 <6a 0.17a 2.0a 2.0a +/-24 <9a Observed DSP 860p Crate Crate Crate CAMAC crate 19 17 20 +6 <50a 20.6a 12.7a 13.0a -6 <50a 23.1a 24.0a 18.0a +/-6 <60a 44a 37a 31a +24 <6a 0.3a 1a 1a -24 <6a 2.1a <7.5a> <8a> +/-24 <9a 2.4a 8.5a 9a +12 0a -12 0a We appear to have a -24v problem. What else is in crates 17 & 20? Fri Apr 13 13:20:59 CDT 2001 summary of psc's BNL trip ---------------------------- - event number (modulo 16) intalled and working in all dyc's - crate power porblems need to be looked at further (Steve thinks that the E949 CAMAC ps are 50amps total for +/-6v). - Request for ~400 more channels of TDC to handle the target looks possible as follows + move VME crate to bottom of controls rack next to its present location + add new CAMAC crate to this location. + request from PREP 12 3377 + 2 DYC's + add to exisiting streams (data volume?) We won't embark on this until there is a real request from the experiment. - Wrote a simple graphical sed from rstdc data in /e949/psc/rstdc_dump* - plan to integrate fast clear/second level trigger in last week of April. - plan to fix 12th module problem in May when beam is off
Trip to BNL 3/12/01-3/14/01: Erik, Sasha, BobT --------------------------- Made the following upgrades to the system: 1) Went from 2 DYCs/1-stream to 6 DYCs on two streams, 3 DYCs/stream. 2) Installed new VME crate in rack, two memories and two DC2s. 3) Removed reliance on MVME-162 and standalone CAMAC. CAMAC init in now from the experiment, and Power-PC reads out memories and and runs our diagnostics. 4) Installed UTNs and DTNs in the back of each rack, UTNs in the back of the VME/DC2 rack and DTNs in the back of the other rack. Summary: Two streams were read independently into two separate DC2s/Memories successfully. DYC/TDC header structure is correct from each DYC. Using RSMON flasher triggers in the evening of 3/13 with HV on we saw TDC data in the raw data dump for 16 channels (1 input data cable) connected to the TDCs. We can see RSMON flasher data there is no need to use test pusler data anymore. Also we can remove the DAWN VME crate, and move the table and terminal back to the nominal place. Naming scheme: Stream 1 - (VME 0e000000ff) - contains DYC 1-3 Stream 2 - (VME 0c000000df) - contains DYC 4-6 DYC 1 - contains TDC x00 - x05 DYC 2 - contains TDC x06 - x0b DYC 3 - contains TDC x0c - x11 DYC 4 - contains TDC x12 - x17 DYC 5 - contains TDC x18 - x1d DYC 6 - contains TDC x1e - x23 TDC 1e and 12 are not being readout. Remaining issues and problems: 1) Two TDC modules are not in the readout, causing two nominal groups of six TDCs to be five TDCs. (Nominal system is 6 sets of 6 TDCs). This is a FERA readout problem for those TDCs groups, and we have swapped: TDCs, DYCs, FERA data cable, slot location of disabled TDC among the six. This looks like some kind of 5 .vs. 6 module termination/load issue, and remains unresolved. 2) The MPI fast-clear/fast-clear-gate logic is not installed, and we cannot run with Level-2 triggers until that is done. Level-1 is good for now we are told. 3) Our REN-PASS chains on 4 DYC groups is built from single jumpers which has reliability problems. We should replace this on our next trip. 4) We DO NOT have spares of the following: DC2s, DTNs, UTNs. We need to bring a spare of each next time. 5) On the next trip we should send back the VME162, INDY & terminal. 6) There isn't powerPC code yet for two-stream readout, Rene is working on it. 7) We do not yet have a solution for how to patch a 4-bit event ordinal into the RS-485 10-pin header on the DYC front panels. we need an elegant level conversion solution.
Thu Dec 14 18:22:50 CST 2000 Begin log book file psc ---------------------------- This is a log book for the Fermilab 3377 TDC system in BNL E949 Thu Dec 14 18:26:27 CST 2000 Status of system psc/bobt ---------------------------- We (bobt and psc) arrived today at 1330. The old fn781b is now bnlku8.phy.bnl.gov {130.199.36.27} The "holy" account is entered with daqe949. Got the system back up and running at the level of one event in a 2 dyc, single dc2 stream. Good things to remember are: on mvme167: @ ! boot ld0x1c00 Test - seems to work. Power cycled VME crate. No problems seen. Fast clears tested by applying gate-gen delayed common stop as fast clear signal. IF delayed more the 4usec (>MPI) runs as normal. If delayed 3us all event readout are suppressed. Fri Dec 15 10:56:09 CST 2000 ---------------------------- Linked a copy of this log-book to the ckm-at-work page of the ckm website behind the usual ckm password. Fri Dec 15 15:33:05 CST 2000 ----------------------------- Replaced the FERA control buses on the two DYCs being used now with harnesses that have an ECL breakout line for the MPI signal. A twisted pair ECL line is connected between the new FERA control buses and a NIM-to-ECL converter. Since the experiment has only a Level-1 trigger now, we test the external MPI by copying the common signal into a gate generator that provides a fast-clear and fast-clear-gate (MPI). We tested the suppression of data (NO DYC readout cycles) as a function of where the fast clear is inside the MPI gate. Readout suppression is seen to behave correctly sweeping from 3-50 usec with a clear signal in a corresponding MPI gate. On system startup on Thursday we saw that TDC(03) (4th TDC) in the first crate was generating test data from the corresponding delay module output even without delay module input! This was traced to a loose cable at the output of the corresponding delay module fanout. Now without delay module inputs only TDC headers are generated in response to a trigger as expected. * * * * * * * * * * Anatomy of NIM bin that handles control and test signals: (slots from the left, viewed from the front) Slots 1&2: Fans out and converts RS TDC "prompt" signal into 16 ECL signals that drive the delay module fanouts in CAMAC crate #17. These signals emulate the data signals. The TDC common signal from the experiment is controlled by a single programmable delay, so that the range of the TDC can be tested by moving the TDC common signal with respect to these test data lines. Slot 3: LRS-222 gate generator that is used to create the MPI "fast-clear-gate" and a fast-clear signal based off of the common signal. This is used for MPI test purposes now. Once the experiment actually has a second level trigger with aborts, then we will receive the real fast-clear-gate and fast-clear from the experiment, and these gate generator channels will be available for any miscellaneous signal stretching. The fast-clear and fast-clear-gate signals will be supplied as ECL signals from the experiment. The ECL->NIM functions in slot #5 described below will be used for these conversions. Slot 4: Phillips 757 fan-in/fanout operating in quad 4X4 mode: quad1: Receives single NIM fast clear from the trigger, distributes up to eight NIM fast clear outputs. Six are required for the six DYCs. quad2: Receives single NIM common stop from the trigger, distributes up to eight NIM common stop outputs. Six are required for the six DYCs. quad3: Receives single NIM fast-clear-gate (MPI) from the trigger and distributes up to eight NIM MPI outputs. Six of these ouputs are converted to ECL in the neighboring NIM->ECL converter, and distributed to the six DYCs. quad4: Available. Slot 5: LRS-4616 NIM/ECL converter. Channels 1-6 receive 6 NIM MPI signals and convert them to ECL, which are then distributed to the six FERA control busses. Channel 7 converts the NIM OR'd DYC BUSY signal to ECL for transport back to the trigger. Channels 8 and 9 are reserved for ECL->NIM conversion function for the fast-clear and fast-clear gate received from the experiment. Channels 10-16 are availble for miscellaneous functions, including NIM signals that can be converted to ECL and sent to the TDC for internal logic time monitoring. Slot 6: Open. Slot 7: LRS-429A, operating in 2X8 mode. The upper half is used by us to fan-in the six DYC busy signals. The single output is sent back to channel #8 of slot 5 for transport back to the trigger. Issues discussed with Rene: 1) At the end of experiment fast-clear there is a 5-microsecond additional hold-off before triggers are enabled again. 2) The trailing edge of the fast-clear-gate (MPI) is generated off the trailing edge of fast-clear with some additional delay. Rene couldn't remember the length of this additional delay. Once we start getting real fast clears and gates we need to measure this. We need to ensure that the fast-clear leading edge be no closer than 100nsec from the end of teh MPI period. This is due to the asynchronous 10 MHz clock that samples the MPI on the TDCs. 200nsec would be a reasonable spec for us here on this MPI closing holdoff. Cables and harnesses to make and bring next time: Situation: 6 DYCs with 6 TDCs each. That's 1152 channels. This would cover the RS+BVL (19+2)*24*2 = 1008 channels. There has been a suggestion of TDC'ing the target as well, but that would be another whopping 512 channels bringing the sum to 1520 channels. This could be accomodated with six DYCs with eight TDCs each which covers 1536 channels. We need to decide about this fairly soon. Whatever we do we should strive to have the harnesses be identical which would mean: Nominal: Data and control harnesses with 6 TDC taps. 6X6 config has three spare TDCs. enhanced: Data and control harnesses with 8 TDC taps. 6X8 config would require and additional six LRS 3377 TDCs to have a pool of 3 spare TDCs. The MPI twisted pair tail is 5 feet long for the two near crates and 7 feet long for the far crate. We should make the tails all be 7 feet long to simplify spares and minimize confusion. The twisted pair tails should be soldered into the control harness MPI line. Maybe we should make the harnesses with eight taps to afford expandability. Fri Dec 15 18:56:21 CST 2000 camac software status psc ---------------------------- George has ported multiTDC to the bnlku7 camac system. /e787/local/online/camac/3377/3377Lib.h /e787/local/online/camac/3377/LRS3377_init.c /e787/local/online/camac/3377/camacLib.h At present the camac works but the change3377mode procedure (which puts each module in common stop-double word mode) fails.