This single-width CAMAC module is designed to act as a combination * bit NIM input-register, LAM generator, trigger-selector, master-inhibit and scaler. All front panel inputs and outputs are NIM. A 16 bit ECL input register with strobe is also available at the auxilary rear connector.
The eight inputs can be individually enabled (via CAMAC or local switches) to cause a LAM to be generated on receit of a NIM signal. Once an input which will produce a LAM is received, further inputs will be ignored (not generate further LAMs) until the module is reset (via CAMAC). The state of the inputs are latched at the time of the trigger and are available via a CAMAC read. An inhibit out is generated from the time of receipt of the first enabled input until the LAM is reset and re-enabled (via CAMAC). The auxiliary rear-connector contains a 17-pair input for ECL signals; the top 16 pairs are received in a latch which is strobed by the 17th pair. These inputs do not generate a LAM.
The following LAM registers, counters and outputs are provided.
A register shows which inputs are "enabled". A NIM signal of at least 20 nanoseconds on any enabled input will generate a LAM, if the LAM itself has been enabled. F(0) A(0) reads this register, F(16) A(0) writes it in "remote mode" or it is set by dip-switches in "local mode". A front panel switch selects the mode. LED's on the front panel indicate which inputs are enabled. A register shows the state of all the inputs 10 ns after the first enabled trigger input. Read with F(1) A(0) lower 8-bits, or F(1) A(2).
A LAM is generated when a signal is received at an enabled input The LAM must be reset F(10) and reenabled F(26), or reset and enabled F(28), for further inputs to generate LAMs. There is a small delay (60 ns minimum, but which can be increased by installing a capacitor) between the receipt of the LAM re-enable and the actual re-enabling of the trigger inputs to prevent a new LAM being generated before the system is really ready to receive one.
A 16 bit ECL input register and strobe is available at the auxilliary connector, the input register is a transparent D type latch which is latched after the occurance of a pulse on the strobe input pins. This register can be read with F(0) A(1), and reset with F(9) A(1), or read and reset with F(2) A(1).
A counter counts the nuymber of LAMS generated. It's read with F(1) A(0) R9-R16, reset with F(11) A(0), or read and reset with F(4) A(0). This allows a check that the system sees the same number of LAMS as the module generates. A counter counts the "or" of all the inputs wether the module is enabled or not. This counter is always live independent of wether a LAM is being proccessed or not, however the value is latched at the time a LAM is generated. After reset of the LAM the current value of the counter can be read. Read with F(1) A(1), reset with F(11) A(1), or read and reset with F(4) A(1). This allows a measure of "live" time.
A pulse ~ 60 ns wide is provided on the TRIG OUT when an input is received which will produce a LAM. This pulse is delayed by 20 ns from the triggering input.
NIM levels are provided on the INHIBIT OUTPUTS from the time that an enabled input is received until the LAM is reenabled.
An input ENABLE IN is provided to allow the module to be ENABLED by an externally applied NIM level. If an external enable is not being used ENABLE IN must be connected to ENABLE OUT.
In a system that requires two modules, the ENABLE IN's should be cross connected to the ENABLE OUT's. For the two modules to be reenabled simultaneously the output cable length should equal the delay time (delay from a CAMAC enable to the actual enable) of the generating module.
Front panel description:
CAMAC op codes - return X and Q immediately except F(16) A(0) when set to local control, and F(8) when LAM is not present.