jorway 84 picture


The Jorway Model 84 QUAD Scaler is a single-width, high-speed CAMAC compatible module which meets the requirements of EUR 4100e. It features a discriminator front-end to provide reliable counting, independent of input waveshape. Inputs are fully protected against transients, and the Scaler will count pulses as narrow as 3 nsec, at rates in excess of 100 MHz ( 125MHz typical). Buffered, open-collector, carry outputs are provided which may be wired to patch pins if desired. Data is read out on the CAMAC dataway upon receipt of appropriate command.

All functions are fully decoded to provide unique responses to commands. A Q response is generated for each Read, Clear and Test command. Scaler input gating is controlled by either the dataway Inhibit or via a front panel, high-speed inhibit input. The latter inputs are bridged to permit "daisey chaining" between scalers. Under no circumstances will an inhibit signal cause the scalers to count. Front panel lights indicate when the module is addressed (N) and when tile scaler gate is open.

Several options are available which enable the Model 84 to perform a number of additional functions.

1 . Overflow flip-flops for each channel can be added. These allow an overflow flip-flop to be triggered at either the overflow of 1-it 15 or bit 23, and be read out on the Dataway on the appropriate read line ( Rl 6 or R24). These overflows may also be wired to open collector buffers for readout on patch pins.

2. The unit may be used as a 4-channel time interval meter by simply adding a jumper, which allows the inhibit input to function as a count input. Thus, by applying the signal to be timed to one of the channel inputs, and injecting the clock into the inhibit input ( common to all channels), each channel will now count the clock as long as its input signal is present. A clock as high as 100 MHz may be used, providing a resolution of 10 nsec.

3. The Q response for Clear (F9) and Test (F25) commands may be disabled.

4. Two bridged, front panel LEMO connectors for reset input can be supplied in lieu of the manual reset pushbutton. SPECIFICATIONS MODEL 84 QUAD SCALER


 SIGNAL INPUT (each Channel)
   Pulse Repetition Rate           0-100 mpps min. (125 mpps typical)
   Pulse Pair Resolution           10 nsec. min.
   Minimum Pulse Width            3 nsec.
   Discriminator Level            -500mv (Internally adj. to a min.
                        -300 mv)
   Input  Impedance            50 Ohm +/- 1% D. C. coupled
   Input  Protection            +/- 5Ov Transients

 CAPACITY                   24 Binary Bits (16,777,215 pulses)

 INHIBIT INPUT (common to all Channels)    Two bridged LEMO connectors on
                        front panel. Bridged inputs allow
                        "daisy chaining" of inhibit signal
                        from scaler to scaler.
   Input  Impedance            5K min.
   Sensitivity                -500mv
   Input  Protection            +/- 50v transients
   Response Time               Less than 10 nsec.

   Gate Selector               Two position locking toggle switch
                        allows gating to be controlled in one
                        position by the front panel inhibit
                        signal or in the other position by the
                        front panel inhibit signal "OR"ed
                        with dataway inhibit (I).
   Manual Reset               Front panel pushbutton clears all
                        channels simultaneously.

 DATAWAY COMMANDS (all fully decoded)
   N-FO-AO                  Read Scaler 1
   N-FO-Al                  Read Scaler 2
   N-FO-AZ                  Read Scaler 3
   N-FO-A3                  Read Scaler 4
   N-F9-AO-S2                Clear Scaler 1
   N-F9-A1-S2                Clear Scaler 2
   N-F9-A2-S2                Clear Scaler 3
   N-F9-A3-S2                Clear Scaler 4
   N-F25-(AO+Al+A2+A3)-S2          Test

  Initialize         Z-S2 Clear all scalers & overflows
  Clear          C-S2 Clear all scalers & overflows
  Inhibit          I  Controls gating of all channels
               when front panel gating switch
               is in appropriate position.

  Carry          A 1 us. (min. ) carry pulse is generated
             for each channel whenever a scaler
             exceeds its capacity. This signal has
             transition times greater than 2OO nsec
             so that it may be applied to the patch
  Data           24 bits read out on the read lines on
             command. Least significant digit is

  Q Response         Q=1 for: N-FO-(AO+A1+A2+A3) and
             N-F9-(AO+A1+A2+A3) and

    The Q response for F9 and F25 may be deleted.

  N Light          Indicates when a module is addressed,
             this signal is integrated so it will in-
             dicate even if addressed for a short
  Gate Light         Indicates when the counting gates are
             open and the unit will count input
             signals that exceed the threshold.

 POWER REQUIREMENTS        +6V @ 700 ma nominal.
             -6V @ 550 ma nominal.

 TEMPERATURE RANGE         0'- 60'C

 SIZE            Single CAMAC width, with protective
             side shields.

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