Gate and Delay Generators are designed to provide precisely timed logic windows and level transitions. Applica tions employing Gate and Delay Generators may require that a logic transition occur immediately and have a given duration. Others require that a delay elapse prior to the logic transition, or that a precise gate be generated after some fixed delay. All these functions of Gate Generator, Delay Generator, and Delayed Gate Generator are performed by any LeCroy Gate and Delay Generator module.
LeCroy Gate and Delay Generators allow both manual and CAMAC programmability for gate durations ranging from a few nanoseconds to several seconds. Both the 2323A and the 4222 can be used for burst mode operations with the TR8828D digitizer (see Application Note 2014).
Minimum Dead Time - Any of these Gate and Delay Generators may be retriggered immediately after the delay has elapsed.
Delayed Outputs - At the end of any gate, a delayed output issues a pulse.
Independent Gate and Delay Functions - Each LeCroy Gate and Delay Generator provides precision gate lengths which can be used as a precision delay as well. Since each unit has at least two such gate generators, one can be used as a delay which starts the second generator that provides the gate signal.
Wide Dynamic Range - Ranges from under 100 nsec to 10 sec are provided by the Model 2323A. Model 4222 maintains 1 nsec resolution up to its range of 16.7 msec.
The Model 2323A is a fully programmable Gate and Delay Generator packaged with 2 channels in a double-width CAMAC module. Its Gate duration is programmable over the range 100 nsec to 10 seconds, covering a dynamic range of eight orders of magnitude. Moreover, outputs as short as 50 nsec can be selected at the expense of accuracy and stability. All settings may be programmed under CAMAC control or via front-panel controls. The settings of the instrument are battery backed-up, so the unit does not have to be reprogrammed after turning the crate off/on or after a power failure. The 2323A offers excellent stability and jitter properties with 0.2% of Full Scale accuracy in the gate setting.
The 2323A offers both Start and Stop inputs. This allows the output pulse width to be determined by the Start -Stop time difference in the latched mode or by the internal timer in the preset mode. A Blanking NIM Level input causes a notch to be taken out of the gate, equal in duration to the Blanking input. This is especially useful to gate off data acquisition during spurious periods. Conversely, a NIM level OR input causes all outputs to be set to True for the duration of the OR inputs.
The unit offers NIM and NIM level outputs equal in duration to the gate width selected. In addition, a DELAY output is produced at the trailing edge of the Gate pulse. The 2323A also provides a differential ECL output and a TTL output capable of driving a NIM Bin Gate. Both the ECL and TTL outputs may be driven from either the Gate or Delay circuit. These options are selected by board-mounted shorting plugs.
The Gate duration and the width of the Delayed output are both programmable under CAMAC control. Each of the two channels are programmed independently. All values which are loaded into the 2323A may also be read back via CAMAC. Programming the delay involves a 10-bit "mantissa" and a 3-bit "characteristic".
The Start input is normally configured to accept NIM level signals. A bridged high impedance input is employed to allow the trigger of more than one channel of 2323A. The front end of the Start input consists of a comparator circuit, factory adjusted to trigger at -400 ±50 mV. A front-panel accessed multiple turn potentiometer allows the user to adjust the threshold over the range -3 V to +3 V. This allows the unit to be triggered by NIM, ECL, TTL or other standard logic signals. A front-panel accessed switch selects either the positive-going or negative-going edge as the trigger. The stop input accepts NIM standard pulses.
START: Bridged high impedance pair. Lemo-type connectors. Input trigger level adjustable over the range ±3 V via front-panel potentiometer, supplied at -400 ±50 mV with a negative-going edge. This input initiates the timing cycle.
STOP: Standard NIM input, Lemo-type connectors. This input terminates the timing cycle in the latched mode. Active in both latched and preset modes. The delay is < 20 nsec.
OR: Standard NIM input, Lemo-type connector. Input impedance 50 ohm. Produces outputs as long as the OR signal is asserted.
BLANK: Standard NIM input, Lemo-type connector. Input impedance 50 ohm. Cancels gate outputs as long as the BLANK signal is asserted. Overrides OR input.
BUSY LED: Indicates unit is active.
NIM: Standard NIM (-16 mA) signal, Lemo-type connector. Goes low for gate duration. Rise time 2 nsec; fall time 2.5 nsec.
NIM*: Standard NIM (-16 mA) signal, Lemo-type connector. Goes high for gate duration. Rise time 2 nsec; fall time 2.5 nsec.
ECL: Complementary ECL levels, 2-pin connector. PC-mounted shorting plug allows this output to be logically identical to the GATE or DELAY pulse or their complements.
TTL: An FET open drain output (250 mA, 0.5 W maximum). PC-mounted shorting plug allows this output to be logically identical to the GATE or DELAY pulse or their complements.
DELAY: Standard NIM (-16 mA) signal, Lemo-type connector. Delayed from start of NIM by the gate width. (Goes low at trailing edge of gate.) Programmable for 10, 30, 100 or 300 nsec duration. Rise time 2 nsec.
Range: 100 nsec to 10 sec (50 nsec width at reduced accuracy and stability).
Accuracy: ±0.2% of full scale.
Temperature Stability: < 200 ppm/°C.
Jitter: < 0.3% of setting.
Resolution: 0.1% of full scale.
Width Options: 10 nsec, 30 nsec, 100 nsec, 300 nsec.
Input-Output Delay: 24 nsec (Start input to NIM output).
Recovery Time: None. The unit may be retriggered any time after the timing cycle has been completed.
Packaging: Double-width module in conformance with CAMAC Standard; ESONE Report EUR4100 or IEEE Report #583. RF-shielded.
Power Requirements: 1.8 A at +6 V; 1.3 A at -6 V; 50 mA at +24 V; 75 mA at -24 V; 21.6 W total.
C or Z: Stops channels A and B gates.
X: X response is generated for each valid function.
Q: Q response is generated for each valid function unless otherwise specified.
CAMAC FUNCTION CODES
F(1)·A(0): Read channel A programming word.
F(1)·A(1): Read channel B programming word.
F(9)·A(0): Stop channel A gate.
F(9)·A(1): Stop channel B gate.
F(17)·A(0): Write channel A programming word.
F(17)·A(1): Write channel B programming word.
F(25)·A(0): Start channel A gate.
F(25)·A(1): Start channel B gate.
The CAMAC programming word is 16 bits wide and is divieded up into four
|W16 ... W15||W14||W13 ... W11||W10 ... W1|
The first 10 bits, W1 - W10, are the mantissa (M). This number, seen in the 3-1/2 digit front panel display, ranges from 0 to 1023.
The next 3 bits, W11 - W13, ar ethe characteristic (C). It sets the order of magnitude of the gate duration.
The next bit, W14, is the latch bit (L). When L=0, the gate duration equals M*10^C nSec. Settings of M below 100 will result in somewhat reduced accuracy and stability. When L=1, the gate duration equals the time between the STOP and START.
The next bits, W15 - W16, determine the delay width (D).
The CAMAC START and STOP commands perform the same function as the external START and STOP input.
the CAMAC C or Z commands shut down both outputs simultaneously.
NOTE: In the CAMAC mode, the TRIGGER switches ans the threshold pots have no effect.