The basic strategy implemented is to generate a common stop for every accept and reject, and clear the common stop with a fast clear within the MPI for Level-1.n rejects. This strategy forces EVERY Level-1.n accept and reject to require at least 10 microseconds (RSTDC common stop time) so that the common stop can be processed by MPI logic that only initiates upon receipt of common stop. This does increase the deadtime for rejects that arrive before the common stop, but has the advantage of simplicity. Based on Level-1.n rate information from Steve, this scheme will increase the deadtime by 0.2% for the "Hex-afterburner" rejects that come a few hundred nanoseconds after Level-0. The balance of Level-1.1 and Level-1.2 rejects arrive 10-20+ microseconds after Level-0. Erik has proposed a scheme which clears RSTDC readout from early (less than 10 microsecends) fast clears by vetoing the generation of the RSTDC common stop for these early rejects. These scheme however gets tricky for rejects that arrive very close in time to the RSTDC common stop (10 usec), and there is no guarantee that rejects will not come then.
The external MPI gate is started with RSTDC common stop, and is stopped by a logical "OR" of delayed copies of "Trigger accept" (SSP start) and the Level-1.n fast clear. The trigger accept is delayed 12 microseconds, so that if the accept is generated before the RSTDC stop, then the trailing MPI edge is guaranteed to occur after the RSTDC stop. This is a hardwired time that we have to be conscious of if we change the RSTDC stop time. Since we expect the RSTDCs will finish readout before the other streams, this small delay should not contribute to overall detector deadtime. To deal with Level-1.n fast clears that arrive before the RSTDC stop, George has built a circuit that latches an early fast clear and re-issues it 250 nsec after the RSTDC stop time. The trailing edge of MPI generated from fast clears is issued 400 nsec after the fast clear time.
We have tested the MPI logic running with all triggers accepted and all triggers rejects over external MPI gate durations of 650 nsec (minimum) to 400 microseconds. We have extensively tested running with all fast clears coming very near to the RSTDC common stop time. Unfortunately we were not able to reasonably test a mix of accepts and rejects since the Level-1.n generator board now can't support a mix now.
This logic requires that each trigger have an associated accept or reject. Since the RSTDC common stop is generated at by Level-0, any Level-0 trigger that doesn't have an attendant accept or reject (indecisive) will hang the system. This is the current problem with the Level-1.n board, it often doesn't generate an appropriate "trigger done" state. In commissioning the MPI logic we discovered that trigger initialization generates a RSTDC stop without an attendant trigger decision, which leaves the MPI gate hanging open. The origin of this problem hasn't been tracked down yet, but to protect from it we have installed a 50 millisecond timeout on the MPI gate. When the MPI times out, an event will percolate through to the DC2s, but the DC2s are cleared at run initialization which occurs normally after trigger initialization. For the future it probably would be a good idea to add a DC2 and DYC clear to the tail end of trigger initialization as well.